Title :
A Multiple Media Delay Simulator for MOS LSI Circuits
Author :
Okazaki, Kaoru ; Moriya, Tomoko ; Yahara, Toshihiko
Author_Institution :
LSI Research and Development Laboratory, Mitsubishi Electric Corporation, Hyogo, Japan
Abstract :
This paper concerns an accurate delay modeling of MOS gates at the logic level. The model takes account of the effects of not only the loading capacitance but also the slope of the input waveform. A logic simulator which uses multiple rise/fall delays based on the model is described. Some experimental results are also presented.
Keywords :
Capacitance; Circuit simulation; Delay effects; Large scale integration; Logic circuits; Logic devices; Propagation delay; Switches; Threshold voltage; Timing;
Conference_Titel :
Design Automation, 1983. 20th Conference on
Print_ISBN :
0-8186-0026-8
DOI :
10.1109/DAC.1983.1585663
