Timing Analysis for nMOS VLSI

TV and IA are timing analysis programs for nMOS VLSI designs. Based on the circuit obtained from existing circuit extractors, TV determines the minimum clock duty and cycle times. It calculates the direction of signal flow through all transistors before the timing analysis is performed. The timing analysis is breadth-first (block-oriented) and pattern independent, using the values stable, rise, fall, as well as information about clock qualification. TV has fast running time, small user input requirements, and the ability to offer the user valuable advice. IA (TV´s Interactive Advisor) allows the user to quickly experiment with ways to increase circuit performance. Several delay models can be used; when compared to circuit simulation and fabricated chips, accuracies within 20% for most critical paths have been achieved.