Symmetrical triple-threshold-voltage nine-transistor SRAM circuit with superior noise immunity and overall electrical quality

Data stability is a major concern in today´s high performance memory circuits with deeply scaled transistors and power supply voltages. Multi-threshold-voltage (multi-V_t) nine-transistor (9T) Static Random Access Memory (SRAM) cells with enhanced data stability and superior overall electrical quality characteristics are presented in this paper. 9T SRAM cells eliminate the data disturbance by isolating the bitlines from data storage nodes during read operations. The design tradeoffs of 9T multi-V_t SRAM cells are explored with a TSMC 65nm CMOS technology that provides a rich set of device threshold voltage options. A triple-threshold-voltage 9T memory cell offers up to 9.7X higher overall electrical quality as compared to a previously published single-threshold-voltage 9T SRAM cell.