DocumentCode
3147448
Title
A scalable multi-ASIP architecture for standard compliant trellis decoding
Author
Brehm, Christian ; Ilnseher, Thomas ; Wehn, Norbert
Author_Institution
Microelectron. Syst. Design Res. Group, Univ. of Kaiserslautern, Kaiserslautern, Germany
fYear
2011
fDate
17-18 Nov. 2011
Firstpage
349
Lastpage
352
Abstract
Multi standard wireless modems are already becoming more and more important in industry. The recent move for LTE will aggravate this issue. We present a heterogeneous channel decoding architecture, which contains a scalable multi-ASIP cluster to support multiple legacy standards, while being able to offload the bulk of LTE decoding to an heavily optimized decoder to achieve a very good power efficiency. The energy efficiency in a 65 nm process node is 0.3 nj/bit/iter for LTE turbo code decoding and 0.69 nj/bit/iter for legacy standards.
Keywords
Long Term Evolution; channel coding; decoding; instruction sets; trellis codes; LTE decoding; heterogeneous channel decoding; multiple legacy standards; multistandard wireless modems; optimized decoder; scalable multiASIP architecture; scalable multiASIP cluster; size 65 nm; standard compliant trellis decoding; ASIP; Core; LTE; MPSoC; Multi Core; Processor; SDR; Turbo Code; UMTS; Viterbi; standard-driven;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference (ISOCC), 2011 International
Conference_Location
Jeju
Print_ISBN
978-1-4577-0709-4
Electronic_ISBN
978-1-4577-0710-0
Type
conf
DOI
10.1109/ISOCC.2011.6138782
Filename
6138782
Link To Document