DocumentCode :
3148501
Title :
Average and maximum power consumption of digital CMOS circuits using LOGIC PICTURES
Author :
Fouda, M.F. ; Abdelhalim, M.B. ; Amer, H.H.
Author_Institution :
Electron. & Commun. Dept., Cairo Univ., Giza, Egypt
fYear :
2009
fDate :
14-16 Dec. 2009
Firstpage :
225
Lastpage :
230
Abstract :
In this paper, a new methodology is developed to calculate the exact value of both the average and the maximum power consumptions of combinational circuits. The main advantage of this methodology over other techniques reported in the literature is its accuracy. It depends on a new concept called logic pictures. A logic picture is the set of logic values at all gate outputs in the circuit for a given input vector. To verify the correctness of the methodology, it was applied to three circuits from well-known benchmarks as well as commercial ICs. The average and maximum power consumptions obtained were identical to those produced by exhaustive simulation.
Keywords :
CMOS logic circuits; benchmark testing; combinational circuits; integrated circuit modelling; power consumption; benchmarks; combinational circuits; commercial ICs; digital CMOS circuits; exhaustive simulation; gate outputs; input vector; logic pictures; logic values; power consumption; CMOS digital integrated circuits; CMOS logic circuits; Circuit simulation; Combinational circuits; Computational modeling; Energy consumption; Logic circuits; Power dissipation; Power engineering and energy; SPICE; CMOS; Combinational logic circuits; Power consumption; Toggle rate;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Engineering & Systems, 2009. ICCES 2009. International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-5842-4
Electronic_ISBN :
978-1-4244-5843-1
Type :
conf
DOI :
10.1109/ICCES.2009.5383280
Filename :
5383280
Link To Document :
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