Title :
A radiation hard 1750 μP fabricated on improved silicon on sapphire
Author :
Kerr, J.A. ; Garraway, A. ; Shaw, C.M. ; Wootten, D.
Author_Institution :
GEC Plessey Semiconductors, Lincoln, UK
Abstract :
Describes work carried out at GEC Semiconductors on an improved silicon on sapphire fabrication process and it´s application to advanced VLSI circuits. The experimental silicon on sapphire material matrix studied included various sapphire substrate preepitaxy annealing schedules, coupled with variable epitaxial deposition temperatures and rates. In addition, both Union Carbide and Kyocera supplied substrates were compared. The results of material analysis together with pre- and post-radiation electrical data will be presented. A dramatic reduction in post-radiation leakage levels on both test transistors and associated SRAM circuits is demonstrated. A single chip 1750 μP has been fabricated in the GEC Semiconductors 1.5 μm SOS process using this improved material specification. The performance of the first iteration of this processor before and after irradiation is described
Keywords :
SRAM chips; VLSI; annealing; field effect integrated circuits; microprocessor chips; radiation hardening (electronics); semiconductor epitaxial layers; 1.5 micron; 1750 microprocessor; GEC Semiconductors; SOS fabrication process; SOS process; SRAM circuits; VLSI; epitaxial deposition temperatures; material analysis; post-radiation electrical data; post-radiation leakage levels; pre-radiation electrical data; preepitaxy annealing schedules; Annealing; Circuit testing; Coupling circuits; Fabrication; Random access memory; Semiconductor materials; Silicon; Substrates; Temperature; Very large scale integration;
Conference_Titel :
Radiation and its Effects on Devices and Systems, 1991. RADECS 91., First European Conference on
Conference_Location :
La Grande-Motte
Print_ISBN :
0-7803-0208-7
DOI :
10.1109/RADECS.1991.213640
