Functional Design Verification by Multi-Level Simulation

This paper introduces Intel´s functional CAD design environment and methodology. The generation of an accurate behavioral model for use in systems design validation and for comparisons with lower-level components is described. The need for both an RTL and a schematics simulator in Intel´s hierarchical design methodology is explained. Finally, the paper shows how these two simulators have been linked together in two ways for two different purposes: for RTL-schematics verification, and for very large logic simulation runs.