Techniques to improve memory interface test quality for complex SoCs

Aggressive speed and voltage binning schemes are widely used in the industry to improve the yield of SoCs. For accurate bin classification, it is essential that the tests used for binning target the worst critical/speed-limiting paths in the design. We have observed in many SoCs that memory interface paths are amongst the top critical paths. In this paper, we propose new DFT schemes to improve the quality of memory interface logic test. We also discuss practical challenges and propose solutions for successfully implementing ATPG on memory-interface paths of large SoCs. Experimental results on 40nm industrial designs show an average increase of 36% memory interface fault coverage. Fmax result from production SoC silicon establishes the effectiveness of the proposed scheme for speed binning.