Digital implementation of discrete-time cellular neural networks with distributed arithmetic

We propose an efficient digital architecture for the discrete-time cellular neural networks (DTCNNs). That is based on the combination of the bit-serial computation of distributed arithmetic (DA) with the characteristics of the DTCNN: the local connectivity and the translation invariance in the templates. Implementation of the DTCNN with the proposed architecture requires a reduced hardware complexity and a small number of bus lines. It consumes less silicon area because of the bit-serial computation of DA and offers higher speed operation than the analog implementations of the DTCNN. A DTCNN cell was implemented in a 0.8 μm CMOS technology. The experimental results show that the maximum operation frequency of chip is 30 MHz