Title :
Array Test Structure for Ultra-Thin Gate Oxide Degradation Issues
Author :
Hafkemeyer, Kristian M. ; Domdey, Andreas ; Schroeder, Dietmar ; Krautschneider, Wolfgang H.
Author_Institution :
Inst. of Nanoelectron., Hamburg Univ. of Technol., Hamburg
fDate :
March 30 2009-April 2 2009
Abstract :
An array test structure for highly parallelized measurements of ultra-thin MOS gate oxide failures caused by degradation is presented. The test structure allows for voltage stress tests of several thousand NMOS devices under test (DUTs) in parallel to provide a large and significant statistical base regarding soft as well as hard breakdown and stress induced degradation of transistor parameters. The array has been fabricated in a standard 130 nm CMOS technology. As mixed mode technologies provide both thin and thick oxide MOS transistors, different gate oxide thicknesses have been chosen for DUTs and digital control logic which gives the possibility to stress the DUTs with high gate voltages.
Keywords :
CMOS integrated circuits; MOSFET; failure analysis; semiconductor device breakdown; semiconductor device testing; 130 nm CMOS technology; NMOS DUT; NMOS device under test; array test structure; device breakdown; digital control logic; mixed mode technology; size 130 nm; thick oxide MOS transistor; transistor parameters; ultrathin MOS gate oxide failure; ultrathin gate oxide degradation; voltage stress test; Breakdown voltage; CMOS logic circuits; CMOS technology; Degradation; Electric breakdown; MOSFETs; Stress; Temperature; Testing; Tunneling;
Conference_Titel :
Microelectronic Test Structures, 2009. ICMTS 2009. IEEE International Conference on
Conference_Location :
Oxnard, CA
Print_ISBN :
978-1-4244-4259-1
DOI :
10.1109/ICMTS.2009.4814616
