DocumentCode :
3153405
Title :
Functional Fault Modeling and Simulation for VLSI Devices
Author :
Gupta, Anil K. ; Armstrong, James R.
Author_Institution :
Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA
fYear :
1985
fDate :
23-26 June 1985
Firstpage :
720
Lastpage :
726
Abstract :
Functional fault modeling and simulation for VLSI devices is described(*). A functional fault list is compiled using model perturbation and mapping of circuit defects into functional faults. A set of test vectors is then derived which detects all faults in the functional fault list. This same test vector set is then applied to a gate level model of the device. For the test case analyzed, a very high level of equivalent gate coverage was achieved. Conclusions are drawn as to the effectiveness of the technique and how amenable it is to automation.
Keywords :
Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Fabrication; Logic design; Logic testing; Semiconductor device modeling; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1985. 22nd Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0635-5
Type :
conf
DOI :
10.1109/DAC.1985.1586022
Filename :
1586022
Link To Document :
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