Algorithms for Automatic Transistor Sizing in CMOS Digital Circuits

This paper describes the algorithms for automatic transistor sizing (determination of device width and length) of CMOS digital circuits. In CMOS circuits, since power dissipation is small and not a limiting factor, the sizing algorithm is geared toward minimizing area. The program XTRAS (Xerox TRAnsistor Sizing Program) which determines transistor sizes as well as calculates path delays is described. Equations for the calculation of gate area, node capacitances, and rise and fall delays are given. Example circuits sized using XTRAS are compared and found to be within 10% of SPICE circuit simulations.