Title :
Scaling tunneling oxide to 50Å in floating-gate logic NVM at 65nm and beyond
Author :
Wang, Bin ; Niset, Martin ; Ma, Yanjun ; Nguyen, Hoc ; Paul, Ron
Author_Institution :
Impinj Inc., Seattle
Abstract :
Logic NVM using I/O gate oxide as storage floating gate dielectric developed in baseline logic process does not require extra masks or process steps. Conventional wisdom has suggested that the tunnel oxide of Flash will reach its scaling limits at 6-7 nm due to high reliability requirement for high-density applications. Will FG logic NVM be scalable with tunneling oxide down to 50 A of 2.5 V I/O devices at technology nodes of 65 nm and beyond? In this work, we demonstrate that FG logic NVM with 50 A is readily achievable by performing theoretical statistics analysis and utilizing advanced reliability engineering. Reliability data on FG logic NVM with 50 A tunneling oxide in a standard 65 nm CMOS technology process is also provided.
Keywords :
integrated circuit reliability; integrated logic circuits; logic gates; random-access storage; floating-gate logic; logic NVM; reliability engineering; scaling tunneling oxide; CMOS logic circuits; CMOS process; CMOS technology; Logic arrays; Logic devices; Logic programming; Nonvolatile memory; Reliability engineering; Statistical analysis; Tunneling;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2007. IRW 2007. IEEE International
Conference_Location :
S. Lake Tahoe, CA
Print_ISBN :
978-1-4244-1771-9
Electronic_ISBN :
1930-8841
DOI :
10.1109/IRWS.2007.4469220