Title :
A reliability study in P-channel punchthrough for ASIC CMOS input/output buffer leakage
Author_Institution :
Atmel Corp., Colorado Springs
Abstract :
Quite simply, does CMOS punchthrough leakage current present a reliability risk? Does this form of leakage accelerate any other failure mechanisms or alter device performance within the circuit? This paper empirically answers these questions while providing an academic understanding of the mechanism and why it dose not pose a reliability risk.
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit reliability; leakage currents; ASIC CMOS leakage current; failure mechanism; p-channel punchthrough; reliability study; Acceleration; Application specific integrated circuits; Driver circuits; Failure analysis; Leakage current; MOSFETs; Springs; Testing; Threshold voltage; Transistors;
Conference_Titel :
Integrated Reliability Workshop Final Report, 2007. IRW 2007. IEEE International
Conference_Location :
S. Lake Tahoe, CA
Print_ISBN :
978-1-4244-1771-9
Electronic_ISBN :
1930-8841
DOI :
10.1109/IRWS.2007.4469241
