DocumentCode
3154263
Title
A New Algorithm for Floorplan Design
Author
Wong, D.F. ; Liu, C.L.
Author_Institution
Department of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
fYear
1986
fDate
29-2 June 1986
Firstpage
101
Lastpage
107
Abstract
We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in the final solution. Experimental results indicate that the algorithm performs well in many test problems.
Keywords
Algorithm design and analysis; Computational modeling; Computer science; Computer simulation; Design methodology; Integrated circuit interconnections; Minimization; Performance evaluation; Shape; Simulated annealing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1986. 23rd Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0702-5
Type
conf
DOI
10.1109/DAC.1986.1586075
Filename
1586075
Link To Document