SCAT - A New Statistical Timing Verifier in a Silicon Compiler System

The program SCAT is a new timing verifier within the ALGIC silicon compiler. It provides a precise assessment of the timing behaviour of the automatically generated LSI circuits by means of block-oriented statistical algorithms leading to a running time approximately linear to the number of circuit elements, which are emulated by delay time elements. Interconnect delays are handled by the same statistical model. Synchronous circuits are described by an appropriate coordinate transformation leading to an algorithm for the calculation of the minimum clock period. The special case of recursive structures is briefly mentioned.