Transistor-Level Test Generation for Physical Failures in CMOS Circuits

A new methodology is proposed for generating tests at the transistor level for realistic failures including bridging faults, and transistor gate-to-source short and gate-to-drain short faults in CMOS combinational circuits. A new tree model for a fault-free CMOS complex gate is used to propagate errors due to faults with much less computation time. The technique adapts the tree structure representation for MOS gates to the D-Algorithm.