A Technology Independent Approach to Hierarchical IC Layout Extraction

This Paper describes a set of heuristics for a hierarchical circuit extractor. The strength of these algorithms lies in their capability for fully exploiting the natural hierarchical structure of IC Layouts, and in handling overlapping cell instances without creating partial devices. Technology independence is implemented by keeping all technology dependent information in a user accessible file external to the program, which is also used to define the extent of parameter extraction. Circuit extraction is performed in a bottom-up manner and produces a netlist description with the same hierarchical structure as the Layout.