Noise analysis in ultra high speed CMOS track and hold circuit

Author

Liang, Hailang ; Evans, Rob J. ; Skafidas, Efstratios

Author_Institution

Dept. of Electr. & Electron. Eng., Univ. of Melbourne, Melbourne, VIC, Australia

fYear

2009

fDate

Jan. 9 2009-Dec. 11 2009

Firstpage

330

Lastpage

334

Abstract

Noise performance of the switched source follower (SSF) track and hold (T/H) circuit is analyzed. Approximate expressions for the output noise of the track mode and hold mode of the T/H circuit are derived respectively. Simulations based on a commercial available 65 nm process technology are implemented with the SpectreRF circuit simulator. It is shown that the noise contribution from the parasitic capacitance is significant at ultra high frequency and the dominant noise of the SSF T/H circuit is the KT/C thermal noise. Simulations also indicate that noise contribution in track mode is more than that in hold mode and locate the major noise contributor in the SSF T/H circuit.

Keywords

CMOS analogue integrated circuits; circuit simulation; integrated circuit noise; sample and hold circuits; 65 nm process technology; KT/C thermal noise; SpectreRF circuit simulator; hold mode; noise analysis; parasitic capacitance; size 65 nm; switched source follower track and hold circuit; track mode; ultra high speed CMOS track and hold circuit; 1f noise; Capacitors; Circuit noise; Circuit simulation; Dynamic range; Frequency; Switches; Switching circuits; Tail; Voltage; CMOS switched source follower; Track and hold amplifier; noise location; noise suppression and noise model; ultra high speed;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio-Frequency Integration Technology, 2009. RFIT 2009. IEEE International Symposium on

Conference_Location

Singapore

Print_ISBN

978-1-4244-5031-2

Electronic_ISBN

978-1-4244-5032-9

Type

conf

DOI

10.1109/RFIT.2009.5383727

Filename

5383727