A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applications

We propose a pipelined division architecture for low-power ECC applications, which is based on partial-division on group basis and lookahead technique exploiting the linearity in finite field arithmetic. The throughput is one division per clock regardless of the degree of the dividend polynomial. The salient feature of this architecture is that it leads to very low power-delay product. To verify the relative performance of the proposed division architecture over the conventional one using LFSR, three RS and BCH code applications were fabricated using 0.8 /spl mu/m double metal CMOS technology. Experimental results show about 32, 65, 67 times improvement in power consumption compared with conventional one using LFSR.