Node normalization and decomposition in low power technology mapping

Author

Noth, W. ; Kolla, Reiner

Author_Institution

Lerstuhl fur Technische Inf., Wurzburg Univ., Germany

fYear

1997

fDate

18-20 Aug. 1997

Firstpage

275

Lastpage

280

Abstract

In CMOS technology the decomposition of the nodes of a circuit can significantly reduce the circuit power dissipation. We present a normalization algorithm which extracts the largest nodes of the given netlist. Then we examine a known node decomposition algorithm and propose a new one which is provable optimal and tractable for moderate node sizes. Reduction of the overall switching activity on standard benchmark circuits is shown for exact (ROBDD) and uncorrelated signal probabilities.

Keywords

Boolean functions; CMOS logic circuits; circuit CAD; combinational circuits; high level synthesis; integrated circuit design; CMOS technology; ROBDD; binary decision diagrams; circuit power dissipation; low power technology mapping; netlist; node decomposition algorithm; node normalization algorithm; reduced order BDD; switching activity reduction; uncorrelated signal probabilities; Boolean functions; CMOS technology; Circuit simulation; Circuit synthesis; Data structures; Delay; Energy consumption; Permission; Signal synthesis; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-89791-903-3

Type

conf

Filename

621298