• DocumentCode
    315656
  • Title

    Exploring module selection space for architectural synthesis of low power designs

  • Author

    Shen, Z.X. ; Jong, C.C.

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore
  • Volume
    3
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    1532
  • Abstract
    Architectural synthesis for low power design is a complex optimization problem due to the interdependence of power, delay and area. In order to obtain the optimal low power architecture where both the delay and area are efficient, full design space of module selection must be explored. In this paper we formulate the module selection as a multi-objective optimization problem and propose a branch and bound approach to explore the large design space of module selection. Experiments show that this approach can produce far better results than traditional architectural synthesizers where power, delay and area are all globally optimized simultaneously
  • Keywords
    high level synthesis; modules; optimisation; architectural synthesis; area; delay; low power design; module selection space; multi-objective optimization; Circuits; Delay; Design optimization; High level synthesis; Libraries; Scheduling; Space exploration; Space technology; Synthesizers; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.621420
  • Filename
    621420