Buffered single-phase clocked logic for high-speed CMOS pipelined circuits

Author

Kim, Seokjin ; Sridhar, Ramalingam

Author_Institution

Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1900

Abstract

This paper presents a pseudo single-phase clocked CMOS dynamic logic style called Buffered Single-Phase Clocked (BSPC) logic for high-speed pipelined circuits. The use of buffered straight-line clock distribution methods eliminates the need for the slow P-type transistors in the true single-phase clocking (TSPC) logic. Thus further speed improvement of TSPC has been achieved while maintaining the advantages of using a single-phase clock. The clocking constraints are described. An 8 b adder with reverse clock distribution has been designed in a 0.5 μm CMOS technology which operates at a clock rate of up to 1.33 GHz

Keywords

CMOS logic circuits; adders; pipeline processing; timing; 0.5 micron; 1.33 GHz; 8 bit; CMOS dynamic logic style; adder; buffered single-phase clocked logic; clocking constraints; high-speed CMOS pipelined circuits; pseudo single-phase clocked logic; reverse clock distribution; speed improvement; submicron CMOS technology; Adders; CMOS logic circuits; CMOS technology; Capacitance; Clocks; Delay; Latches; Logic circuits; Logic design; Pulse inverters;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621521

Filename

621521