• DocumentCode
    315696
  • Title

    Improvement in radiation-hard CMOS logic gates for noise margin

  • Author

    Yih, S.-J. ; Chang, M.-L. ; Hwu, J.-G. ; Feng, W.-S.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    3
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    1916
  • Abstract
    A design technique for fundamental CMOS logic gates that are almost insensitive to noise margin is proposed. An auxiliary circuit is added to the conventional CMOS logic gates. All the circuits are simulated by HSPICE. It is observed from simulation results that good radiation hard behavior appears in the improved inverter, NOR and NAND gates for noise margin, especially for the scaling down on supply voltage VDD
  • Keywords
    CMOS logic circuits; SPICE; circuit analysis computing; combinational circuits; integrated circuit design; integrated circuit noise; logic CAD; logic gates; radiation hardening (electronics); HSPICE simulation; NAND gates; NOR gates; auxiliary circuit; design technique; inverter; noise margin; radiation-hard CMOS logic gates; supply voltage scaling; CMOS logic circuits; CMOS technology; Circuit noise; Circuit simulation; Circuit synthesis; Inverters; Logic gates; MOS devices; MOSFET circuits; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.621525
  • Filename
    621525
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=315696