DocumentCode
315697
Title
Whole-chip ESD protection design for submicron CMOS VLSI
Author
Ker, Ming-Dou ; Liu, Shue-Chang
Author_Institution
VLSI Design Dept., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Volume
3
fYear
1997
fDate
9-12 Jun 1997
Firstpage
1920
Abstract
A VDD-to-VSS ESD clamp circuit is designed to provide the real whole-chip ESD protection for submicron CMOS IC´s. The ESD-protection efficiency is experimentally verified to be dependent on the pin location of a chip. This whole-chip ESD protection design has been successfully implemented in a 0.8-μm CMOS IC product with a real pin-to-pin ESD protection of above 3 kV
Keywords
CMOS integrated circuits; VLSI; electrostatic discharge; integrated circuit design; integrated circuit reliability; surge protection; 0.8 micron; 3 kV; VDD-to-VSS ESD clamp circuit; pin location; submicron CMOS VLSI; whole-chip ESD protection design; CMOS integrated circuits; Clamps; Electrostatic discharge; Integrated circuit modeling; MOS devices; Pins; Protection; Variable structure systems; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN
0-7803-3583-X
Type
conf
DOI
10.1109/ISCAS.1997.621526
Filename
621526
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