High speed equalizer architectures based on floating point number representation

For high speed digital communications VLSI signal processors such as those used in VDSL and ATM LAN applications, the logic associated with the feed-forward equalizer taps accounts for much of the silicon area and power dissipation. The paper presents a novel arithmetic unit, which allows one to reduce the size of the multipliers. One of the multiplicands, the data, is stored in fixed point format, while the other, the error (coefficient) is converted in floating point format with a reduced mantissa width. In the case of the error, the coefficient update multiplier can be replaced with a shift and add structure. For the equalizer FIR section, the coefficients are split in sets and the coefficient mantissa width is optimized for each set. This procedure allows one to minimize the quantization noise for a given total coefficient length