A multicasting ATM switch architecture

Author

Seidel, Daniel F. ; Bayoumi, Magdy A.

Author_Institution

Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

2140

Abstract

An architecture for Asynchronous Transfer Mode (ATM) switching with an aggregate capacity approaching 10 Gb/s and 160 Gb/s for the entire switching fabric is described in this paper. The architecture provides a minimum delay variation for each packet in a multicast stream. The entire system is designed from the ground up to allow for a growable network with an emphasis on simplicity and modularity. The switching nodes have 16 inputs and 16 outputs and, to facilitate the scalability of the switching fabric, the nodes both utilize and generate backpressure flow-control information for switching element neighbors. Full ATM line speed is retained at 622 Mb/s

Keywords

B-ISDN; asynchronous transfer mode; delays; packet switching; 10 Gbit/s; 160 Gbit/s; 622 Mbit/s; ATM line speed; B-ISDN; aggregate capacity; backpressure flow-control information; growable network; minimum delay variation; multicasting ATM switch architecture; packet switching; scalability; switching element neighbors; switching fabric; switching nodes; Aggregates; Asynchronous transfer mode; B-ISDN; Computer architecture; Delay; Fabrics; Multiprocessor interconnection networks; Packet switching; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621593

Filename

621593