Retiming of latches for power reduction of DSP designs

In this paper a retiming methodology is proposed which reduces the power consumption of digital CMOS circuits. The application of high level synthesis tool for arbitrary designs usually leads to the usage of edge triggered registers. However, VLSI implementations of DSP algorithms which are considered here make level sensitive registers applicable. Level sensitive registers consist of two latches which store the data for half a clock period. If these latches are placed separately in the circuit then, glitching can be reduced and single latches can store data on the gate capacity of the logic instead of the gate of additional inverters. These two effects reduce the power dissipation of the total circuit and savings of the considered DSP implementation up to 20% or more have been achieved