Novel PSO based FPGA placement techniques

Digital ICs for electronic systems are fast realized on Field programmable gate array (FPGA). The reconfigurability of FPGA has made this mode of digital circuit synthesis more popular among the system designers. But unlike other ICs it provides a restricted hardware structure for circuit implementation and hence the computer aided design (CAD) software is also constrained. The placement being a very vital step in the design process needs to be performed optimally for high performance circuits. In this work novel techniques for placement based on simple particle swarm optimization (PSO), constricted PSO and time varying inertia weight (TVIW) PSO are proposed taking bounding box cost into consideration. The results of simulation reveal a competitive performance of the circuits implemented. The technique proposed here also offer faster convergence to a placement solution. The performance of a single BCD counter circuit is studied in details by using the different PSO algorithms. The netlist generated from the Xilinx design tool is used for placement and optimization results are reported here.