A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based On An Interleaved Synchronous Mirror Delay Scheme

Author

Saeki, T. ; Nakamura, H. ; Shimizu, J.

Author_Institution

NEC Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211, Japan

fYear

1997

fDate

12-14 June 1997

Firstpage

109

Lastpage

110

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on

Print_ISBN

4-930813-76-X

Type

DOI

10.1109/VLSIC.1997.623831

Filename

623831

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