Design of parallel BCH decoder for MLC memory

BCH (Bose-Chaudhuri-Hocquenghem) coding is very useful to correct a small bit error. But the code length n is longer such as a game program stored in a MLC (multi-level cell) flash memory, the decoding circuits takes a lot of computation time. This paper presents a parallel decoding architecture of BCH coding aiming to speed up that guarantees 2-bit error correction. It allows one word data can be fed into the BCH decoder at a time and decoded in parallel. The experimental results show that the proposed (4122, 4096, 2) BCH decoder runs about 7.5 times faster than the binary counterpart even though it has 1.2 times area overhead.