Title :
A 3D, physically based compact model for IC VDMOS transistors
Author :
Victory, James ; McAndrew, Colin ; Thoma, Rainer
Author_Institution :
Motorola Inc., Geneva, Switzerland
Abstract :
A 3D VDMOS model has been derived and implemented in Pspice. The geometry dependent model includes accurate, scalable models for the gate-charge, including the voltage-varying gate-drain capacitance and the distributed effects of the buried layer and metal resistances on the total on-resistance of the device
Keywords :
SPICE; buried layers; capacitance; electric resistance; power MOSFET; semiconductor device models; 3D physically based compact model; Pspice; VDMOS transistors; accurate scalable models; buried layer; distributed effects; gate-charge; geometry dependent model; metal resistances; smart power ICs; total on-resistance; voltage-varying gate-drain capacitance; Capacitance; Displays; Fingers; Integrated circuit modeling; MOSFET circuits; Power MOSFET; Power control; SPICE; Semiconductor process modeling; Voltage;
Conference_Titel :
Microelectronics, 1997. Proceedings., 1997 21st International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-3664-X
DOI :
10.1109/ICMEL.1997.625278
