DocumentCode :
3162543
Title :
Logic Verification Methodology for PowerPC ™ Microprocessors
Author :
Charles H.Malley, Max Dieudonne
Author_Institution :
Motorola Inc., Austin, TX
fYear :
1995
fDate :
12-16 June 1995
Firstpage :
234
Lastpage :
240
Abstract :
The PowerPC logic verification methodology is a general purpose approach suitable for a large class of chip designs that can exceed five million transistors in size. Several validation techniques are integrated into an automated logic verification strategy. The success of this methodology has been demonstrated by realizing three PowerPC microprocessor chips that were functional the first time.
Keywords :
Automatic test pattern generation; Boolean functions; Chip scale packaging; Circuit faults; Circuit synthesis; Circuit testing; Integrated circuit interconnections; Logic circuits; Logic design; Microprocessors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
0-89791-725-1
Type :
conf
DOI :
10.1109/DAC.1995.250096
Filename :
1586708
Link To Document :
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