Title :
Maximizing speed performance of multi-level combinational circuits implemented with pass transistors
Author :
Neves, José Luis P Correia
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
Abstract :
Speed optimization techniques are presented in this paper to reduce the propagation delay through multi-level combinational circuits. The circuits are built with a set of CMOS logic gates designed upon pass transistors and transmission gates. The speed optimization techniques include determining the order of connecting the input pins of the gates, determining the minimum number of inverters to reduce the propagation delay and determining the inverter insertion points within the circuit. Circuits designed with the new set of logic gates and optimized with the aforementioned techniques performed up to four times faster than the same circuits designed with two-input static NAND/NOR gates
Keywords :
CMOS logic circuits; circuit optimisation; combinational circuits; logic design; multivalued logic circuits; CMOS logic gates; inverter insertion points; multi-level combinational circuit; pass transistors; propagation delay; speed optimization; transmission gates; CMOS logic circuits; Combinational circuits; Design optimization; Inverters; Joining processes; Logic circuits; Logic design; Logic gates; Pins; Propagation delay;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551954
