DocumentCode :
3163042
Title :
A novel slotted-ring architecture for parallel processing: an application
Author :
Yaremchuk, George ; Pon, Carlos R. ; Kwasniewski, Tad ; Goubran, Rafik
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
fYear :
1994
fDate :
25-28 Sep 1994
Firstpage :
486
Abstract :
A novel efficient bus architecture is presented together with an application. The bus architecture belongs to a slotted-ring class. 32-bits of data, l4-bits address, and signalling buses span across a maximum of sixteen processors configured in a ring. The bus information arriving at each processing element can be either: passed without change, captured by the processing element (PE) and/or overwritten by the PE. The delay through each PE is 30 ns when using 1989 IC technology. Through the use of newer IC technology and due to unique physical arrangement of the bus the delay time can be reduced to approximately 15 ns. Through the use of time slot arrangements and/or signalling lines the data can reach any of the other processors in the system. Logically each processor sees the memory of the other as part of a global write-only memory. The unique hardware processor internal synchronization mechanism reduces the synchronization overhead. This paper presents implementation details of the hardware as well an application in the iterative solution of dense linear equations as the test-bed multiprocessor
Keywords :
iterative methods; matrix algebra; multiprocessor interconnection networks; parallel architectures; synchronisation; system buses; 14 bit; 15 ns; 30 ns; 32 bit; DSP algorithms; IC technology; address bus; bus architecture; data bus; delay time; dense linear equations; global write-only memory; hardware processor internal synchronization; iterative solution; matrix equation; parallel processing; processing element; ring processors; signalling bus; signalling lines; slotted-ring architecture; synchronization overhead reduction; test-bed multiprocessor; time slot arrangements; Data buses; Iterative methods; Matrices; Multiprocessor interconnection; Parallel architectures; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on
Conference_Location :
Halifax, NS
Print_ISBN :
0-7803-2416-1
Type :
conf
DOI :
10.1109/CCECE.1994.405794
Filename :
405794
Link To Document :
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