Title :
Hardware module selection for real time pipeline architectures using probabilistic cost estimation
Author :
Sentieys, O. ; Diguet, J. Ph ; Philippe, J.L. ; Martin, E.
Author_Institution :
LASTI-ENSSAT, Lannion, France
Abstract :
Module selection is a basic task of architectural synthesis which aims to optimize the cost of dedicated circuits. However, this task remains unresolved in the case of synthesizing pipeline architectures under real time constraint using a complex library exploiting multifunctional, pipeline, and multi-delay operators. This paper presents a new formalization and implementation of module selection integrated in the GAUT tool. The cost function used is based on the area of selected components and a probabilistic estimation of the area of registers, bus, and interconnections. It includes some results in the field of real time digital signal processing
Keywords :
application specific integrated circuits; circuit CAD; delays; high level synthesis; integrated circuit design; logic CAD; parallel architectures; real-time systems; GAUT tool; architectural synthesis; complex library; dedicated circuits; hardware module selection; interconnections; multi-delay operators; probabilistic cost estimation; real time digital signal processing; real time pipeline architectures; registers; Control system synthesis; Cost function; Digital signal processing; Hardware; High level synthesis; Integrated circuit synthesis; Libraries; Logic design; Pipelines; Signal synthesis;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551981
