Title :
A generic system simulator (GENESYS) for ASIC technology and architecture beyond 2001
Author :
Eble, John C. ; De, Vivek K. ; Wills, D Scott ; Meindl, James D.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
Abstract :
GENESYS, a hierarchical tool for exploring future ASIC technology and architecture, is described and employed to project high-performance ASIC power drain and clock frequency, a roadmap for interconnect design, and performance, energy, and area limits
Keywords :
application specific integrated circuits; integrated circuit modelling; integrated circuit technology; technological forecasting; ASIC technology; GENESYS; architecture; generic system simulator; hierarchical tool; Application specific integrated circuits; Clocks; Computer architecture; Delay; Frequency; Integrated circuit interconnections; Microelectronics; Packaging; Power system modeling; Space technology;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551992
