Title :
Sampling based design verification using design error models
Author_Institution :
Dept. of Electr. Eng., Yonsei Univ., Seoul, South Korea
Abstract :
A new simulation based design verification system employing design error models and statistical sampling techniques, is developed. It provides a simulation coverage which can be used as a guide in the verification process, and estimates the coverage quickly using sampling techniques. The simulation results demonstrate the effectiveness of this approach. This system can be used as an efficient design verification tool to reduce the overall design cycle time
Keywords :
errors; integrated circuit design; cycle time; design verification; error model; simulation coverage; statistical sampling; Application specific integrated circuits; Circuit faults; Circuit simulation; Computational modeling; Computer errors; Costs; Digital systems; Process design; Sampling methods; Test pattern generators;
Conference_Titel :
ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-3302-0
DOI :
10.1109/ASIC.1996.551993
