Title :
HDL driven chip layout within the FHDL design framework
Author :
Morency, Craig D. ; Maurer, Peter M. ; Wang, Zhicheng
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Abstract :
Techniques of automatically generating layout from Florida Hardware Design Language (FHDL) specifications are presented. These techniques allow for the automated layout of read-only memories (ROMs) and programmable logic arrays (PLAs), and they allow for the user-assisted automatic layout of standard-cell blocks. Adaptations of the FHDL and its framework to permit layout synthesis are presented. Cell generation is discussed. Adapting the simulation framework and primitive simulation modelling are discussed
Keywords :
circuit layout CAD; integrated circuit technology; logic CAD; logic arrays; read-only storage; specification languages; CAD; FHDL design framework; Florida Hardware Design Language; HDL driven chip layout; IC design; PLAs; ROMs; automated layout; cell generation; layout synthesis; primitive simulation modelling; programmable logic arrays; read-only memories; specifications; standard-cell blocks; Central Processing Unit; Circuit synthesis; Computer languages; Delay; Hardware design languages; Integrated circuit synthesis; Packaging; Programmable logic arrays; Read only memory; Routing;
Conference_Titel :
Southeastcon '90. Proceedings., IEEE
Conference_Location :
New Orleans, LA
DOI :
10.1109/SECON.1990.117851
