DocumentCode :
3163954
Title :
An Algorithm for Incremental Timing Analysis
Author :
Jin-fuw Lee, Donald T. Tang
Author_Institution :
IBM Thomas J. Watson Research Center, Yorktown Heights, NY
fYear :
1995
fDate :
1995
Firstpage :
696
Lastpage :
701
Abstract :
In recent years, many new algorithms have been proposed for performing a complete timing analysis of sequential logic circuits. In this paper, we present an incremental timing analysis algorithm. When an incremental design change is made on the logic network, this algorithm will identify the portion of design for which the timing is affected, and quickly derive the new arrival times and slacks. A fast incremental timing analysis is desirable for users doing interactive logic design. It is particularly important for a logic synthesis program, which needs to evaluate the circuit delays under many logic modifications.
Keywords :
Algorithm design and analysis; Clocks; Delay; Latches; Logic circuits; Logic design; Pattern analysis; Performance analysis; Sequential circuits; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1995. DAC '95. 32nd Conference on
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
0-89791-725-1
Type :
conf
DOI :
10.1109/DAC.1995.250054
Filename :
1586791
Link To Document :
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