DocumentCode
3164158
Title
An alternative algorithm for high speed multiplication and addition using growing technique
Author
Hashemian, Reza
Author_Institution
Dept. of Electr. Eng., Northern Illinois Univ., De Kalb, IL, USA
fYear
1992
fDate
28-29 Feb 1992
Firstpage
124
Lastpage
129
Abstract
An alternative algorithm is presented for multiplication/addition of variable bit-size operands. The algorithm is shown to be fast, and the computational time is variable and dependent on the accuracy requested. The growing nature of the product term, during the course of operation, gives the method some unique computational properties. The algorithm is implemented for the design of 32×32-bit multiplier
Keywords
digital arithmetic; multiplying circuits; high speed multiplication; multiplier; variable bit-size operands; Algorithm design and analysis; Clocks; Counting circuits; Digital filters; Digital integrated circuits; Hardware; Manipulator dynamics; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1992., Proceedings of the Second Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-2610-0
Type
conf
DOI
10.1109/GLSV.1992.218355
Filename
218355
Link To Document