Title :
Si nanoprocess for vertical double-gate MOSFET fabrication
Author :
Masahara, M. ; Matsukawa, T. ; Ishii, K. ; Yongxun Liu ; Sakamoto, K. ; Kanemaru, S. ; Suzuki, E.
Author_Institution :
Nanoelectronics Res. Inst., Nat. Inst. of AIST, Ibaraki, Japan
Abstract :
Key processes for the vertical DG MOSFET fabrication, (1) ultrathin Si wall formation, (2) double side gate formation, and (3) contact hole opening on the top of the ultrathin Si wall, were proposed.
Keywords :
MOSFET; elemental semiconductors; nanotechnology; silicon; Si; Si nanoprocess; contact hole opening; double side gate formation; ultrathin Si wall formation; vertical double-gate MOSFET fabrication; Anisotropic magnetoresistance; CMOS process; CMOS technology; Erbium; Etching; Fabrication; Interference; Lithography; MOSFET circuits; Resists;
Conference_Titel :
Microprocesses and Nanotechnology Conference, 2002. Digest of Papers. Microprocesses and Nanotechnology 2002. 2002 International
Conference_Location :
Tokyo, Japan
Print_ISBN :
4-89114-031-3
DOI :
10.1109/IMNC.2002.1178572
