DocumentCode :
3164898
Title :
An 8 b 40 MHz CMOS subranging ADC with pipelined wideband S/H
Author :
Ishikawa, Masayuki ; Tsukahara, Tsuneo
Author_Institution :
NTT, Atsugi, Japan
fYear :
1989
fDate :
15-17 Feb. 1989
Firstpage :
12
Lastpage :
13
Abstract :
The authors describe an 8-b CMOS subranging ADC (analog/digital converter) with a 40-MHz conversion rate and a 30-MHz effective resolution bandwidth. The subranging architecture makes it possible to produce small ADCs for digital video applications. A combined DAC (digital/analog converter)/subtractor architecture is used to improve the conversion rate and linearity, a bandwidth enhancement technique is employed for a high-precision integrator-type S/H (sample and hold), and a pipelined S/H and comparator architecture is used to improve the conversion rate. A block diagram of the subranging ADC is shown. A micrograph of an ADC chip fabricated using 1- mu m CMOS technology is presented. The chip achieves effective bits of 7.9, 7.3, and 6.5 at 10-MHz, 30-MHz, and 40-MHz sampling rates, respectively, and full-scale input voltages.<>
Keywords :
CMOS integrated circuits; analogue-digital conversion; digital integrated circuits; pipeline processing; video signals; 1 micron; 30 MHz; 8 bit; CMOS subranging ADC; DAC/subtractor architecture; analog/digital converter; bandwidth enhancement; conversion rate; digital video applications; effective resolution bandwidth; full-scale input voltages; micrograph; pipelined wideband S/H; sampling rates; subranging architecture; Bandwidth; CMOS technology; Differential amplifiers; Large scale integration; Linearity; Radio frequency; Sampling methods; Switches; Voltage; Wideband;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1989.48212
Filename :
48212
Link To Document :
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