Title :
A 50 MHz 24 b floating-point DSP
Author :
Shimazu, Y. ; Kengaku, T. ; Fujiyama, T. ; Teraoka, E. ; Ohno, T. ; Tokuda, T. ; Tomisawa, O. ; Tsujimichi, S.
Author_Institution :
Mitsubishi, Hyogo, Japan
Abstract :
A 24-bit floating-point digital signal processor (DSP) has been developed primarily for speech processing and communication applications. The chip uses 1.0- mu m double-metal CMOS with tungsten silicide technology. The instruction set is upward compatible with an 18-bit DSP. Novel circuit design techniques allowing 40-ns machine cycle time at 50-MHz clock and less than 600-mW power dissipation are described. A built-in self-test is prepared using on-chip IROM and the two 24-bit linear feedback shift registers which are included in I/O registers such as the data register, the serial input registers, and the serial output registers. The DSP design features are summarized.<>
Keywords :
CMOS integrated circuits; digital arithmetic; digital signal processing chips; speech analysis and processing; 1 micron; 24 bit; 40 ns; 50 MHz; 600 mW; I/O registers; WSi/sub 2/ technology; built-in self-test; circuit design techniques; clock frequency; communication applications; data register; double-metal CMOS; floating-point digital signal processor; instruction set; linear feedback shift registers; machine cycle time; on-chip IROM; power dissipation; serial input registers; serial output registers; speech processing; CMOS technology; Circuit synthesis; Clocks; Digital signal processing; Digital signal processing chips; Digital signal processors; Registers; Silicides; Speech processing; Tungsten;
Conference_Titel :
Solid-State Circuits Conference, 1989. Digest of Technical Papers. 36th ISSCC., 1989 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1989.48226
