Optimizing CMOS combinatorial circuits using multiple attribute decision making techniques

Author

Kechichian, K. ; Al-Khalili, A.J. ; Al-Khalili, D.

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

fYear

1994

fDate

25-28 Sep 1994

Firstpage

549

Abstract

In VLSI CMOS circuit design chip area, signal propagation delay and power dissipation are conflicting criteria that need to be optimized in order to improve performance. Full circuit simulation and manual optimization can be costly and time consuming. We present here a method of obtaining different circuit configurations from a given multiple-output Boolean expression. An optimum circuit is selected from the solution space using a multiple attribute decision making (MADM) technique

Keywords

Boolean functions; CMOS logic circuits; VLSI; circuit CAD; circuit analysis computing; circuit optimisation; combinational circuits; CMOS combinatorial circuits; VLSI CMOS circuit design; chip area; circuit configurations; circuit optimization; circuit simulation; multiple attribute decision making techniques; multiple-output Boolean expression; power dissipation; signal propagation delay; solution space; Boolean functions; CMOSFET logic devices; Circuit optimization; Circuit simulation; Combinational logic circuits; Decision-making; Design automation; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 1994. Conference Proceedings. 1994 Canadian Conference on

Conference_Location

Halifax, NS

Print_ISBN

0-7803-2416-1

Type

conf

DOI

10.1109/CCECE.1994.405810

Filename

405810