Title :
Test generation for gate level sequential machines: algorithms and implementation issues
Author :
Macii, E. ; Lioy, A. ; Meo, A.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
Abstract :
Algorithms and implementation issues concerning a Boolean factorization based test generation package for gate level sequential machines are discussed. Practical aspects like justification and propagation weights computation and targeted test pattern generation are treated in depth, giving both theoretical and pseudo-code solutions. The experimental results showed that the proposed method was effective in generating sufficiently high fault coverage for the standard set of ISCAS´89 benchmark synchronous sequential circuits.<>
Keywords :
Boolean algebra; circuit analysis computing; sequential circuits; sequential machines; Boolean factorization based test generation package; benchmark synchronous sequential circuits; experimental results; gate level sequential machines; high fault coverage; justification; propagation weights computation; pseudo-code solutions; targeted test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Fabrication; Packaging machines; Redundancy; Sequential analysis; Sequential circuits; System testing; Test pattern generators;
Conference_Titel :
CompEuro '92 . 'Computer Systems and Software Engineering',Proceedings.
Conference_Location :
The Hague, Netherlands
Print_ISBN :
0-8186-2760-3
DOI :
10.1109/CMPEUR.1992.218499
