Verilog HDL methodology for redundancy in digital circuits targeting FPGA technology for highly reliable applications

Fault tolerance represents the foundation for critical systems, providing reliable computation and control in a broad range of applications. This is a major area of interest for aerospace and military applications. The need for fault tolerant systems in terrestrial applications is of growing importance also. In such systems, fault tolerance is achieved through redundancy, increasing implementation complexity and costs. This paper presents a methodology for implementing redundant digital circuits using Verilog HDL and targeting FPGA technology. Various redundant digital circuits are presented. For the simulation and implementation of the circuits, Cadence NC and Xilinx design tools were used.