Title :
Session #2 Planar SOI device
Author :
Doris, Bruce ; Fung, Samuel
Author_Institution :
IBM, USA
Keywords :
CMOS process; CMOS technology; MOSFET circuits; Manufacturing processes; Parasitic capacitance; Power MOSFET; Research and development; Semiconductor device manufacture; Stress; Voltage;
Conference_Titel :
SOI Conference, 2008. SOI. IEEE International
Conference_Location :
New Paltz, NY
Print_ISBN :
978-1-4244-1954-8
Electronic_ISBN :
1078-621X
DOI :
10.1109/SOI.2008.4656271
