Application and packaging of the AT&T DSP3 parallel signal processor

Author

Shively, R.R. ; Wu, L.J.

Author_Institution

AT&T Bell Labs., Whippany, NJ, USA

fYear

1992

fDate

4-7 Aug 1992

Firstpage

316

Lastpage

326

Abstract

Achieving the potential performance of highly parallel MIMD processor architectures is critically dependent on both the speed and routing capabilities of the network fabric. The routing network of the AT&T DSP3 processor is described together with an indication of how the 40 megabyte/s links can be configured to meet diverse application requirements. Scaling to very large configurations is aided by compact packaging. Silicon-on-silicon multi-chip modules together with a novel three-dimensional vertical interconnection technology are being used to repackage the DSP3 into the ultra-dense processor

Keywords

digital signal processing chips; packaging; parallel architectures; performance evaluation; AT&T DSP3 parallel signal processor; highly parallel MIMD processor architectures; packaging; performance; routing capabilities; silicon-on-silicon multichip modules; three-dimensional vertical interconnection technology; ultra-dense processor; very large configurations; Application specific integrated circuits; Backplanes; Connectors; Electronics packaging; Fabrics; Integrated circuit interconnections; Microprocessors; Routing; Signal processing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Application Specific Array Processors, 1992. Proceedings of the International Conference on

Conference_Location

Berkeley, CA

ISSN

1063-6862

Print_ISBN

0-8186-2967-3

Type

conf

DOI

10.1109/ASAP.1992.218562

Filename

218562