DocumentCode :
3167779
Title :
Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughput
Author :
Hoang, Phu ; Rabaey, Jan
Author_Institution :
Dept. of Electr. Eng., California Univ., Berkeley, CA, USA
fYear :
1992
fDate :
4-7 Aug 1992
Firstpage :
21
Lastpage :
36
Abstract :
A multiprocessor scheduling algorithm that simultaneously considers pipelining, retiming, parallel execution and hierarchical node decomposition to maximize performance throughput is presented. The algorithm is able to take into account interprocessor communication delays, and memory and processor availability constraints. The results on a set of benchmarks demonstrate the algorithm´s ability to achieve near optimal speedups across a wide range of applications of various types of concurrency, with good scalability with respect to processor count
Keywords :
concurrency control; delays; multiprocessing systems; performance evaluation; scheduling; DSP programs; benchmarks; concurrency; hierarchical node decomposition; hierarchical scheduling; interprocessor communication delays; maximum throughput; multiprocessors; parallel execution; processor availability; retiming; scalability; Concurrent computing; Delay; Digital signal processing; Flow graphs; Multiprocessing systems; Pipeline processing; Processor scheduling; Scheduling algorithm; Signal processing algorithms; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application Specific Array Processors, 1992. Proceedings of the International Conference on
Conference_Location :
Berkeley, CA
ISSN :
1063-6862
Print_ISBN :
0-8186-2967-3
Type :
conf
DOI :
10.1109/ASAP.1992.218584
Filename :
218584
Link To Document :
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